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SH7721 Datasheet(PDF) 997 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 997 Page - Renesas Technology Corp |
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997 / 1524 page ![]() Section 27 A/D Converter Rev. 3.00 Jan. 18, 2008 Page 935 of 1458 REJ09B0033-0300 Bit Bit Name Initial Value R/W Description 7 6 CKS1 CKS0 0 1 R/W R/W Clock Select Selects the A/D conversion time. Clear the ADST bit to 0 before changing the conversion time. 00: Conversion time = 151 states (maximum) 01: Conversion time = 285 states (maximum) 10: Conversion time = 545 states (maximum) 11: Reserved (setting prohibited) When P φ ≥ 16.5 MHz, do not set CKS1 and CKS0 to 00. If set, a sufficient conversion time is not assured, causing inaccurate conversion or abnormal operation. 5 4 MULTI1 MULTI0 0 0 R/W R/W Selects single mode, multi mode, or scan mode. 00: Single mode 01: Reserved (setting prohibited) 10: Multi mode 11: Scan mode 3 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 1 0 CH2 CH1 CH0 0 0 0 R/W R/W R/W Channel Select 2 to 0 (CH2 to CH0) These bits and the MULTI bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Single mode Multi mode or scan mode 000: AN0 AN0 001: AN1 AN0, AN1 010: AN2 AN0 to AN2 011: AN3 AN0 to AN3 100: Reserved (setting prohibited) 101: Reserved (setting prohibited) 110: Reserved (setting prohibited) 111: Reserved (setting prohibited) Note: * Only 0 can be written to clear the flag. |
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