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SH7721 Datasheet(PDF) 1012 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 1012 Page - Renesas Technology Corp |
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1012 / 1524 page ![]() Section 27 A/D Converter Rev. 3.00 Jan. 18, 2008 Page 950 of 1458 REJ09B0033-0300 27.7.7 Notes on Countermeasures to Noise Connect a protective circuit between AVcc and AVss, as shown in figure 27.9, to prevent damage of analog input pins (AN0 to AN3) due to abnormal voltage such as excessive serge. Connect a bypass capacitor that is connected to AVcc and a capacitor for a filter that is connected to AN0 to AN3 to AVss. When a capacitor for a filter is connected, input currents of AN0 to AN3 are averaged, may causing errors. If A/D conversion is frequently performed in scan mode, voltages of analog input pins cause errors when a current that is charged/discharged for capacitance of a sample & hold circuit in the A/D converter is higher than a current that is input through input impedance (Rin). Therefore, determine a circuit constant carefully. 0.01 µF 10 µF AVCC (A/D) AN0 to AN3 AVSS (A/D) This LSI *1 100 Ω 0.1 µF Notes: *1 Values are for reference. R in* 2 *2 R in is input impedance. Figure 27.9 Example of Analog Input Protection Circuit Table 27.5 Analog Input Pin Ratings Item Min Max Unit Analog input capacitance 20 pF Allowable signal-source impedance 5 k Ω |
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