SH7721 datasheet(1035/1524 Pages) RENESAS

1035 / 1524 page

Section 29

PC Card Controller (PCC)

Rev. 3.00 Jan. 18, 2008 Page 973 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial Value R/W

Description

IREQE1

R/W

IREQE0

R/W

PCC0IREQ Request Enable

These bits enable or disable

IREQ interrupt requests

and select the interrupt mode when the PC card

connected to area 6 is the I/O card interface type. Note

that bit 5 (P0IREQ) in the area 6 card status change

and 5 in this register are changed. These bits have no

meaning on the IC memory card interface.

00: IREQ requests are not accepted for the PC card

connected to area 6. Bit 5 in the status change

that indicates the inverse of the

IREQ signal.

01: The level-mode IREQ interrupt request signal is

accepted for the PC card connected to area 6. In

level mode, an interrupt occurs when level 0 of the

signal input from the

IREQ is detected.

10: The pulse-mode IREQ interrupt request signal is

accepted for the PC card connected to area 6. In

pulse mode, an interrupt occurs when a falling edge

from 1 to 0 of the signal input from the

IREQ is

detected.

11: The pulse-mode IREQ interrupt request signal is

accepted for the PC card connected to area 6. In

pulse mode, an interrupt occurs when a rising edge

from 0 to 1 of the signal input from the

IREQ is

detected.

P0SCE

R/W

PCC0 Status Change Enable

When the PC card connected to area 6 is on the I/O

card interface, bit 4 enables or disables the interrupt

request when the value of the BVD1

(STSCHG) is

changed. This bit has no meaning in the IC memory

card interface.

0: No interrupt occurs for the PC card connected to

area 6 regardless of the value of the BVD1

(STSCHG)

1: An interrupt occurs for the PC card connected to

area 6 when the value of the BVD1

(STSCHG) is

changed from 1 to 0

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