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SH7721 Datasheet(PDF) 1031 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 1031 Page - Renesas Technology Corp

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Section 29
PC Card Controller (PCC)
Rev. 3.00 Jan. 18, 2008 Page 969 of 1458
REJ09B0033-0300
29.3.3
Area 6 Card Status Change Register (PCC0CSCR)
PCC0CSCR is an 8-bit readable/writable able register. PCC0CSCR bits are set to 1 by interrupt
sources of the PC card connected to area 6 (only bit 7 can be set to 1 as required). PCC0CSCR is
initialized by a power-on reset but retains its value in a manual reset and in software standby
mode.
Bit
Bit Name
Initial Value
R/W
Description
7
P0SCDI
0
R/W
PCC0 Software Card Detect Change Interrupt
A PCC0 software card detect change interrupt can be generated
by writing 1 to this bit. When this bit is set to 1, the same interrupt
as the PCC0 card detect change interrupt (bit 3 set status) occurs
if bit 3 (PCC0 card detect change enable) in the area 6 card
status change interrupt enable register (PCC0CSCIER) is set to
1. If bit 3 is cleared to 0, no interrupt occurs.
0: No software card detect change interrupt occurs for the PC
card connected to area 6
1: Software card detect change interrupt occurs for the PC card
connected to area 6
6
0
Reserved
This bit is always read as 0. The write value should always be 0.
5
P0IREQ
0
R/W
PCC0IREQ Request
Indicates the interrupt request for the
IREQ pin of the PC card
when the PC card connected to area 6 is the I/O card interface
type. The P0IREQ bit is set to 1 when an interrupt request signal
in pulse mode or level mode is input to the
IREQ. The mode is
selected by bits 5 and 6 (PCC0IREQ interrupt enable bits) in the
area 6 card status change interrupt enable register
(PCC0CSCIER). This bit can be cleared to 0 only in pulse mode.
Write 0 to bit 5 to clear the bit to 0. This bit is not changed if 1 is
written. In level mode, bit 5 is a read-only bit, which reflects the
IREQ state (if the IREQ is low, 1 is read). This bit always reads 0
on the IC memory card interface.
0: No interrupt request on the
IREQ of the PC card when the PC
card is on the I/O card interface
1: An interrupt request on the
IREQ of the PC card has occurred
when the PC card is on the I/O card interface



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