Electronic Components Datasheet Search
  English  ▼

X  

SH7721 Datasheet(PDF) 1055 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 1055 Page - Renesas Technology Corp

Back Button SH7721 Datasheet HTML 1051Page - Renesas Technology Corp SH7721 Datasheet HTML 1052Page - Renesas Technology Corp SH7721 Datasheet HTML 1053Page - Renesas Technology Corp SH7721 Datasheet HTML 1054Page - Renesas Technology Corp SH7721 Datasheet HTML 1055Page - Renesas Technology Corp SH7721 Datasheet HTML 1056Page - Renesas Technology Corp SH7721 Datasheet HTML 1057Page - Renesas Technology Corp SH7721 Datasheet HTML 1058Page - Renesas Technology Corp SH7721 Datasheet HTML 1059Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 1055 / 1524 page
background image
Section 30
SIM Card Module (SIM)
Rev. 3.00 Jan. 18, 2008 Page 993 of 1458
REJ09B0033-0300
Bit
Bit Name
Initial
Value
R/W
Description
5
TE
0
R/W
Transmit Enable
Enables/disables serial transmit operations.
0: Disables transmission*
1
1: Enables transmission*
2*3
Notes: 1. The TDRE flag in SCSSR is fixed to 1.
2. In this state, if transmit data is written to SCTDR,
the transmit operation is initiated. Before setting
the TE bit to 1, the serial mode register
(SCSMR) and smart card mode register
(SCSCMR) must always be set, to determine the
transmit format.
3. Even if the TE bit is cleared to 0, the ERS flag is
unaffected, and the previous state is retained.
4
RE
0
R/W
Receive Enable
Enables/disables serial receive operations.
0: Disables reception*
1
1: Enables reception*
2
Notes: 1. Clearing the RE bit to 0 has no effect on the
RDRF, PER, ERS, ORER, or WAIT_ER flag,
and the previous state is retained.
2. If the start bit is detected in this state, serial
reception is initiated. Before setting the RE bit to
1, SCSMR and SCSCMR must always be set, to
determine the receive format.
3
WAIT_IE
0
R/W
Wait Enable
Enables/disables wait error interrupt requests.
0: Disables wait error interrupt (ERI) requests
1: Enables wait error interrupt (ERI) requests
2
TEIE
0
R/W
Transmit End Interrupt Enable
When transmission ends and the TEND flag is set to 1,
transmit end interrupt (TEI) requests are enabled/disabled.
0: Disables transmit end interrupt (TEI) requests*
1: Enables transmit end interrupt (TEI) requests*
Note: * A TEI can be canceled either by writing transmit
data to SCTDR and clearing the TEND bit, or by
clearing the TEIE bit to 0 after the TDRE flag in
SCSSR is read as 1.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com