SH7721 datasheet(1058/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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1058 / 1524 page

Section 30

SIM Card Module (SIM)

Rev. 3.00 Jan. 18, 2008 Page 996 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

RDRF

R/W

Receive Data Register Full

Indicates that received data is stored in the receive data

0: Indicates that no valid received data is stored in SCRDR

[Clearing conditions]

• On reset

• When data is read from SCRDR

• When 0 is written to RDRF

1: Indicates that valid received data is stored in SCRDR

[Setting condition]

When serial reception is completed normally, and received

data is transferred from SCRSR to SCRDR.

Note: In T = 0 mode, when a parity error is detected during

reception, the SCRDR contents and RDRF flag are

unaffected, and the previous state is retained.

On the other hand, in T = 1 mode, when a parity

error is detected during reception, the received data

is transferred to SCRDR, and the RDRF flag is set to

In both T = 0 and T = 1 modes, even if the RE bit in

the serial control register (SCSCR) is cleared to 0,

the SCRDR contents and RDRF flag are unaffected,

and the previous state is retained.

SH7721 Datasheet(PDF) 1058 Page - Renesas Technology Corp