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SH7721 Datasheet(PDF) 1060 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 1060 Page - Renesas Technology Corp |
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1060 / 1524 page ![]() Section 30 SIM Card Module (SIM) Rev. 3.00 Jan. 18, 2008 Page 998 of 1458 REJ09B0033-0300 Bit Bit Name Initial Value R/W Description 3 PER 0 R/W Parity Error Indicates that a parity error has occurred during reception, resulting in abnormal termination. 0: Indicates that reception is in progress, or that reception was completed normally* 1 [Clearing conditions] • On reset • When 0 is written to the PER bit 1: Indicates that a parity error occurred during reception* 2 [Setting condition] When the sum of 1 bit in the received data and parity bit does not match the even or odd parity specified by the O/E bit in the serial mode register (SCSMR). Notes: 1. When the RE bit in SCSCR is cleared to 0, the PER flag is unaffected, and the previous state is retained. 2. In T = 0 mode, the data received when a parity error occurs is not transferred to SCRDR, and the RDRF flag is not set. On the other hand, in T = 1 mode, the data received when a parity error occurs is transferred to SCRDR, and the RDRF flag is set. When a parity error occurs, the PER flag should be cleared to 0 before the sampling timing for the next parity bit. |
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