SH7721 datasheet(122/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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122 / 1524 page

Section 2

CPU

Rev. 3.00 Jan. 18, 2008 Page 60 of 1458

REJ09B0033-0300

2.5.3

Instruction Formats

Table 2.4 shows the instruction formats, and the meaning of the source and destination operands,

for instructions executed by the CPU core. The meaning of the operands depends on the

instruction code. The following symbols are used in the table.

xxxx:

Instruction code

mmmm:

Source register

nnnn:

Destination register

iiii:

Immediate data

dddd:

Displacement

Table 2.4

CPU Instruction Formats

Instruction Format

Source Operand

Destination

Operand

Sample Instruction

0 type

xxxx xxxx xxxx xxxx



NOP

n type

xxxx nnnn xxxx xxxx



nnnn: register

direct

MOVT

Control register or

system register

nnnn: register

direct

STS

MACH,Rn

Control register or

system register

nnnn: pre-

decrement register

indirect

STC.L

SR,@-Rn

m type

xxxx mmmm xxxx xxxx

mmmm: register

direct

Control register or

system register

LDC

Rm,SR

mmmm: post-

increment register

indirect

Control register or

system register

LDC.L

@Rm+,SR

mmmm: register

indirect



JMP

@Rm

PC-relative using



BRAF

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