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SH7721 Datasheet(PDF) 181 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 181 Page - Renesas Technology Corp

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Section 3 DSP Operating Unit
Rev. 3.00 Jan. 18, 2008 Page 119 of 1458
REJ09B0033-0300
Table 3.18
Correspondence between DSP Instruction Operands and Registers
ALU Operations
Multiply Operations
Register
Sx
Sy
Dz
Du
Se
Sf
Dg
A0
Yes
Yes
Yes
Yes
A1
Yes
Yes
Yes
Yes
Yes
Yes
M0
Yes
Yes
Yes
M1
Yes
Yes
Yes
X0
Yes
Yes
Yes
Yes
Yes
X1
Yes
Yes
Yes
Y0
Yes
Yes
Yes
Yes
Yes
Y1
Yes
Yes
Yes
When writing parallel instructions, the field-B instruction is written first, followed by the field-A
instruction. A sample parallel processing program is shown in figure 3.6.
PADD
PINC
PCMP
DCF
MOVX.W
MOVX.W
MOVX.W
@R4+,
@R5+R8,
@R4,
X0
X0
X1
MOVY.W
MOVY.W
[NOPY]
@R6+,
@R7+,
Y0
Y1
A0,
M1,
M1,
M0,
A1
M0
A0
PMULS X0, Y0, M0
Figure 3.6 Sample Parallel Instruction Program
Square brackets mean that the contents can be omitted.
The no operation instructions NOPX and NOPY can be omitted. For details on the field B in DSP
data operation instructions, refer to section 3.6.4, DSP Operation Instructions.
The DSR register condition code bit (DC) is always updated on the basis of the result of an
unconditional ALU or shift operation instruction. Conditional instructions do not update the DC
bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means
of the CS[2:0] bits in the DSR register. The DC bit update rules are shown in table 3.19.



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