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SH7721 Datasheet(PDF) 191 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 191 Page - Renesas Technology Corp |
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191 / 1524 page ![]() Section 3 DSP Operating Unit Rev. 3.00 Jan. 18, 2008 Page 129 of 1458 REJ09B0033-0300 (2) Negative Value Mode: CS[2:0] = B'001 The DC flag indicates the same value as the MSB of the operation result. When the result is a negative number, the DC bit shows 1. When it is 0 or a positive number, the DC bit shows 0. The ALU always executes 40-bit arithmetic operation, so the sign bit to detect whether positive or negative is always got from the MSB of the operation result regardless of the destination operand. Some examples are shown in figure 3.12. Example 1 Sign bit Guard bits Negative value 1100 0000 +) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1100 0000 0000 0000 0000 0001 Example 2 Sign bit Guard bits Positive value 0011 0000 +) 0000 0000 0000 1000 0000 0000 0000 0000 0000 0001 0011 0000 1000 0000 0000 0001 Figure 3.12 DC Bit Generation Examples in Negative Value Mode (3) Zero Value Mode: CS[2:0] = B'010 The DC flag indicates whether the operation result is 0 or not. When the result is 0, the DC bit shows 1. When it is not 0, the DC bit shows 0. (4) Overflow Mode: CS[2:0] = B'011 The DC bit indicates whether or not overflow occurs in the result. When an operation yields a result beyond the range of the destination register, except the guard-bit parts, the DC bit is set. Even though guard bits are provided in the destination register, the DC bit always indicates the result of when no guard bits are provided. So, the DC bit is always set to 1 if the guard-bit parts are used for large number representation. Some DC bit generation examples in overflow mode are shown in figure 3.13. Example 1 Overflow detecting field Guard bits Overflow case 1111 1111 +) 1111 1111 1111 1000 1111 0000 1111 0000 1111 0000 111111110111111111111111 Example 2 Overflow detecting field Guard bits Non overflow case 1111 1111 +) 1111 1111 1111 1000 1111 0000 1111 0000 1111 0001 111111111000 0000 0000 0000 Figure 3.13 DC Bit Generation Examples in Overflow Mode |
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