Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

SH7721 Datasheet(PDF) 193 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 193 Page - Renesas Technology Corp

Back Button SH7721 Datasheet HTML 189Page - Renesas Technology Corp SH7721 Datasheet HTML 190Page - Renesas Technology Corp SH7721 Datasheet HTML 191Page - Renesas Technology Corp SH7721 Datasheet HTML 192Page - Renesas Technology Corp SH7721 Datasheet HTML 193Page - Renesas Technology Corp SH7721 Datasheet HTML 194Page - Renesas Technology Corp SH7721 Datasheet HTML 195Page - Renesas Technology Corp SH7721 Datasheet HTML 196Page - Renesas Technology Corp SH7721 Datasheet HTML 197Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 193 / 1524 page
background image
Section 3 DSP Operating Unit
Rev. 3.00 Jan. 18, 2008 Page 131 of 1458
REJ09B0033-0300
3.5.5
ALU Integer Operations
Figure 3.14 shows the ALU integer arithmetic operation flow. Table 3.23 shows the variation of
this type of operation. The correspondence between each operand and registers is the same as
ALU fixed-point operations as shown in table 3.22.
31
31
39
Ignored
Cleared to 0
31
39
0
Source 1
0
Destination
ALU
DSR
39
0
Source 2
GT
Z
N
V DC
Guard
Guard
Guard
Figure 3.14 ALU Integer Arithmetic Operation Flow
Table 3.23
Variation of ALU Integer Operations
Mnemonic
Function
Source 1
Source 2
Destination
Sx
+1
Dz
PINC
Increment by 1
+1
Sy
Dz
Sx
–1
Dz
PDEC
Decrement by 1
–1
Sy
Dz
Note:
The ALU integer operations are basically 24-bit operation, the upper 16 bits of the base
precision and 8 bits of the guard-bits parts. So the signed bit is copied to the guard-bit parts
when a register not providing the guard-bit parts is specified as the source operand. When
a register not providing the guard-bit parts is specified as a destination operand, the upper
word excluding the guard bits of the operation result are input into the destination register.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com