SH7721 datasheet(194/1524 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 132 of 1458

REJ09B0033-0300

In ALU integer arithmetic operations, the lower word of the source operand is ignored and the

lower word of the destination operand is automatically cleared. The guard-bit parts are effective in

ALU integer arithmetic operations if they are supported. Others are basically the same operation

as ALU fixed-point arithmetic operations. As shown in table 3.23, however, this type of operation

provides two kinds of instructions only, so that the second operand is actually either +1 or –1.

When a word data is loaded into one of the DSP unit’s registers, it is input as an upper word data.

When a register providing guard bits is specified as an operand, the guard bits are also activated.

These operations, as well as fixed-point operations, are executed in the DSP stage, as shown in

figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is

performed.

Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are

basically updated in accordance with the operation result. This is the same as fixed-point

operations but the lower word of each source and destination operand is not used in order to

generate them. See section 3.5.4, ALU Fixed-Point Arithmetic Operations, for details.

In case of a conditional operation, they are not updated even though the specified condition is true

and the operation is executed. In case of an unconditional operation, they are always updated in

accordance with the operation result. See section 3.5.4, ALU Fixed-Point Arithmetic Operations,

for details.

• Overflow Protection

The S bit in SR is effective for any ALU integer arithmetic operations in DSP unit. See section

3.5.11, Overflow Protection, for details.

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