SH7721 datasheet(201/1524 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 139 of 1458

REJ09B0033-0300

The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]

bits. See the negative value mode part above. The Z bit always indicates the same state as the DC

bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit

always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the

overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed

greater than mode by the CS[2:0] bits. See the signed greater than mode part above.

• Overflow Protection

The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section

3.5.11, Overflow Protection, for details.

(2)

Logical Shift

Figure 3.18 shows the logical shift operation flow.

32 31

16 15

32 31

16 15

Shift out

Cleared to 0

Ignored

Left shift

Right shift

32 31

22 21 16

Imm2

Shift amount data

(source 2)

> = 0

< 0

+16 to -16

DSR

Updated

Figure 3.18 Logical Shift Operation Flow

As shown in figure 3.18, the logical shift operation uses the upper word of the source 1 operand

and the destination operand. The lower word and guard-bit parts are ignored for the source

operand and those of the destination operand are automatically cleared as in the ALU logical

operations. The shift amount is specified by the source 2 operand as an integer data. The source 2

operand can be specified by either the register or immediate operand. The available shift range is

from –16 to +16. Here, a negative value means the right shift, and a positive value means the left

shift. It is possible for any source 2 operand to specify from –32 to +31, but the result is unknown

if an invalid shift value is specified. In case of a shift with an immediate operand instruction, the

source 1 operand must be the same register as the destination’s. These operations are executed in

the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which

memory access is performed.

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