SH7721 datasheet(200/1524 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 138 of 1458

REJ09B0033-0300

Note:

The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the

base precision and eight bits of the guard-bit parts. So the signed bit is copied to the guard-

bit parts when a register not providing the guard-bit parts is specified as the source

operand. When a register not providing the guard-bit parts is specified as a destination

operand, the lower 32 bits of the operation result are input into the destination register.

In this arithmetic shift operation, all bits of the source 1 and destination operands are activated.

The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can

be specified by either a register or immediate operand. The available shift range is from –32 to

+32. Here, a negative value means the right shift, and a positive value means the left shift. It is

possible for any source 2 operand to specify from –64 to +63 but the result is unknown if an

invalid shift value is specified. In case of a shift with an immediate operand instruction, the source

1 operand must be the same register as the destination’s. This operation is executed in the DSP

stage, as shown in figure 3.10 as well as in fixed-point operations. The DSP stage is the same

stage as the MA stage in which memory access is performed.

Every time an arithmetic shift operation is executed, the DC, N, Z, V, and GT bits in DSR are

basically updated in accordance with the operation result. In case of a conditional operation, they

are not updated even though the specified condition is true and the operation is executed. In case

of an unconditional operation, they are always updated in accordance with the operation result.

The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC

bit result is:

1. Carry or Borrow Mode: CS[2:0] = B'000

The DC bit indicates the last shifted out data as the operation result.

2. Negative Value Mode: CS[2:0] = B'001

The DC bit is set to 1 when the operation result is a negative value, and cleared to 0 when the

operation result is zero or a positive value.

3. Zero Value Mode: CS[2:0] = B'010

The DC bit is set when the operation result is zero; otherwise it is cleared.

4. Overflow Mode: CS[2:0] = B'011

The DC bit is set to 1 when an overflow occurs.

5. Signed Greater Than Mode: CS[2:0] = B'100

The DC bit is always cleared to 0.

6. Signed Greater Than or Equal Mode: CS[2:0] = B'101

The DC bit is always cleared to 0.

SH7721 Datasheet(PDF) 200 Page - Renesas Technology Corp