SH7721 datasheet(233/1524 Pages) RENESAS

233 / 1524 page

Section 4 Memory Management Unit (MMU)

Rev. 3.00 Jan. 18, 2008 Page 171 of 1458

REJ09B0033-0300

H'F000 0000

H'F100 0000

H'F200 0000

H'F300 0000

H'F400 0000

H'FFFF FFFF

H'FC00 0000

Reserved

Cache address array

Cache data array

TLB address array

TLB data array

H'E000 0000

Control register area

Figure 4.4 P4 Area

The area from H'F000 0000 to H'F0FF FFFF is for direct access to the cache address array. For

more information, see section 5.4, Memory-Mapped Cache.

The area from H'F100 0000 to H'F1FF FFFF is for direct access to the cache data array. For more

information, see section 5.4, Memory-Mapped Cache.

The area from H'F200 0000 to H'F2FF FFFF is for direct access to the TLB address array. For

more information, see section 4.6, Memory-Mapped TLB.

The area from H'F300 0000 to H'F3FF FFFF is for direct access to the TLB data array. For more

information, see section 4.6, Memory-Mapped TLB.

The area from H'FC00 0000 to H'FFFF FFFF is reserved for registers of the on-chip peripheral

modules. For more information, see section 37, List of Registers.

(e)

Uxy Area

The Uxy area is mapped to the on-chip memory of this LSI. This area is made usable in user mode

when the DSP bit in the SR register is set to 1. In user mode, accessing this area when the DSP bit

is 0 will result in an address error. This area cannot be accessed via the cache and cannot be

address-translated by the TLB. For more information on the Uxy area, see section 6, X/Y

Memory.

SH7721 Datasheet(PDF) 233 Page - Renesas Technology Corp