SH7721 datasheet(254/1524 Pages) RENESAS

254 / 1524 page

Section 4 Memory Management Unit (MMU)

Rev. 3.00 Jan. 18, 2008 Page 192 of 1458

REJ09B0033-0300

• Software (Initial Page Write Handler) Operations

The software must execute the following operations:

A. Retrieve the required page table entry from external memory.

B. Set the D bit of the page table entry in the external memory to 1.

C. Write the value of the PPN field and the PR, SZ, C, D, SH, and V bits of the page table

entry in the external memory to the PTEL register.

D. If using software for way selection for entry replacement, write the desired value to the RC

field in MMUCR.

E. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.

F. Issue the RTE instruction to terminate the handler and return to the instruction stream. The

RTE instruction must be issued after two LDTLB instructions.

4.5.5

MMU Exception in Repeat Loop

If a CPU address error or MMU exception occurs in a specific instruction in the repeat loop, the

SPC may indicate an illegal address or the repeat loop cannot be reexecuted correctly even if the

SPC is correct. Accordingly, if a CPU address error or MMU exception occurs in a specific

instruction in the repeat loop, this LSI generates a specific exception code to set the EXPEVT to

′070 for a TLB miss exception, TLB invalid exception, initial page write exception, and CPU

address error and to H'0D0 for a TLB protection violation exception. In addition, a vector offset

for TLB miss exception is H'100. For details, refer to section 7.4.3, Exception in Repeat Control

Period.

SH7721 Datasheet(PDF) 254 Page - Renesas Technology Corp