SH7721 datasheet(250/1524 Pages) RENESAS

250 / 1524 page

Section 4 Memory Management Unit (MMU)

Rev. 3.00 Jan. 18, 2008 Page 188 of 1458

REJ09B0033-0300

4.5

MMU Exceptions

When the address translation unit of the MMU is enabled, occurrence of the MMU exception is

checked following the CPU address error check. There are four MMU exceptions: TLB miss, TLB

invalid, TLB protection violation, and initial page write, and these MMU exceptions are checked

in this order.

4.5.1

TLB Miss Exception

A TLB miss results when the virtual address and the address array of the selected TLB entry are

compared and no match is found. TLB miss exception processing includes both hardware and

software operations.

• Hardware Operations

In a TLB miss, this hardware executes a set of prescribed operations, as follows:

A. The VPN field of the virtual address causing the exception is written to the PTEH register.

B. The virtual address causing the exception is written to the TEA register.

C. Either exception code H'040 for a load access, or H'060 for a store access, is written to the

EXPEVT register.

D. The PC value indicating the address of the instruction in which the exception occurred is

written to the save program counter (SPC). If the exception occurred in a delay slot, the PC

value indicating the address of the related delayed branch instruction is written to the SPC.

E The contents of the status register (SR) at the time of the exception are written to the save

status register (SSR).

F. The mode (MD) bit in SR is set to 1 to place the privileged mode.

G. The block (BL) bit in SR is set to 1 to mask any further exception requests.

H. The register bank (RB) bit in SR is set to 1.

I. The RC field in the MMU control register (MMUCR) is incremented by 1 when all entries

indexed are valid. When some entries indexed are invalid, the smallest way number of

them is set in RC. The setting priority is way0, way1, way2, and way3.

J. Execution branches to the address obtained by adding the value of the VBR contents and

H'0000 0400 to invoke the user-written TLB miss exception handler.

SH7721 Datasheet(PDF) 250 Page - Renesas Technology Corp