SH7721 datasheet(247/1524 Pages) RENESAS

247 / 1524 page

Section 4 Memory Management Unit (MMU)

Rev. 3.00 Jan. 18, 2008 Page 185 of 1458

REJ09B0033-0300

Figure 4.11 shows the case where the IX bit in MMUCR is 0.

When an MMU exception occurs, the virtual page number of the virtual address that caused the

exception is set in PTEH by hardware. The way is set in the RC bit in MMUCR for each exception

according to the rules (see section 4.2.4, MMU Control Register (MMUCR)). Consequently, if the

LDTLB instruction is issued after setting only PTEL in the MMU exception processing routine,

TLB entry recording is possible. Any TLB entry can be updated by software rewriting of PTEH

and the RC bits in MMUCR.

As the LDTLB instruction changes address translation information, there is a risk of destroying

address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure,

therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an

access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two

instructions after the LDTLB instruction.

VPN(31 to 17)

VPN(11 to 10)

ASID(7 to 0)

VPN

ASID

VPN

SV 0 0 RC 0 TF IX AT

PPN

0V 0 PR SZ C D SH 0

Write

PPN(28 to 10) PR(1 to 0) SZ

D SH

Write

Data array

Address array

Way selection

Way 0 to 3

MMUCR

Index

PTEH register

29 28

PTEL register

Figure 4.11 Operation of LDTLB Instruction

SH7721 Datasheet(PDF) 247 Page - Renesas Technology Corp