SH7721 datasheet(243/1524 Pages) RENESAS

243 / 1524 page

Section 4 Memory Management Unit (MMU)

Rev. 3.00 Jan. 18, 2008 Page 181 of 1458

REJ09B0033-0300

3. There is the possibility of simultaneous TLB hits in more than one way. These hits may occur

depending on the contents of ASID in PTEH when a page to which SH is set 1 is registered in

the TLB in index mode (MMUCR.IX = 1). Therefore a page to which SH is set 1 must not be

registered in index mode. When memory is shared by several processings, different pages must

be registered in each ASID.

The object compared varies depending on the page management information (SZ, SH) in the TLB

entry. It also varies depending on whether the system supports multiple virtual memory or single

virtual memory.

The page-size information determines whether VPN (11 to 10) is compared. VPN (11 to 10) is

compared for 1-kbyte pages (SZ = 0) but not for 4-kbyte pages (SZ = 1).

The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry

are compared. ASIDs are compared when there is no sharing between processes (SH

= 0) but not

when there is sharing (SH

= 1).

When single virtual memory is supported (MMUCR.SV

= 1) and privileged mode is engaged

(SR.MD

= 1), all process resources can be accessed. This means that ASIDs are not compared

when single virtual memory is supported and privileged mode is engaged. The objects of address

comparison are shown in figure 4.10.

SH = 1 or

(SR.MD = 1 and

MMUCR.SV = 1)?

SZ = 0?

No (4-kbyte)

Yes

Yes (1-kbyte)

No (4-kbyte)

Yes (1-kbyte)

Bits compared:

VPN 31 to 17

VPN 11 to 10

Bits compared:

VPN 31 to 17

Bits compared:

VPN 31 to 17

VPN 11 to 10

ASID 7 to 0

Bits compared:

VPN 31 to 17

ASID 7 to 0

Figure 4.10 Objects of Address Comparison

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