SH7721 datasheet(242/1524 Pages) RENESAS

242 / 1524 page

Section 4 Memory Management Unit (MMU)

Rev. 3.00 Jan. 18, 2008 Page 180 of 1458

REJ09B0033-0300

Virtual address

Index

Way 0 to 3

VPN(31 to 17)

VPN(11 to 10)

ASID(7 to 0)

Address array

Data array

PPN(28 to 10) PR(1 to 0) SZ

Figure 4.9 TLB Indexing (IX = 0)

4.3.3

TLB Address Comparison

The results of address comparison determine whether a specific virtual page number is registered

in the TLB. The virtual page number of the virtual address that accesses external memory is

compared to the virtual page number of the indexed TLB entry. The ASID within the PTEH is

compared to the ASID of the indexed TLB entry. All four ways are searched simultaneously. If

the compared values match, and the indexed TLB entry is valid (V bit

= 1), the hit is registered.

It is necessary to have software ensure that TLB hits do not occur simultaneously in more than one

way, as hardware operation is not guaranteed if this occurs. An example of setting which causes

TLB hits to occur simultaneously in more than one way is described below. It is necessary to

ensure that this kind of setting is not made by software.

1. If there are two identical TLB entries with the same VPN and a setting is made such that a

TLB hit is made only by a process with ASID = H'FF when one is in the shared state (SH = 1)

and the other in the non-shared state (SH = 0), then if the ASID in PTEH is set to H'FF, there

is a possibility of simultaneous TLB hits in both these ways.

2. If several entries which have different ASID with the same VPN are registered in single virtual

memory mode, there is the possibility of simultaneous TLB hits in more than one way when

accessing the corresponding page in privileged mode. Several entries with the same VPN must

not be registered in single virtual memory mode.

SH7721 Datasheet(PDF) 242 Page - Renesas Technology Corp