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SH7721 Datasheet(PDF) 241 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 241 Page - Renesas Technology Corp

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Section 4 Memory Management Unit (MMU)
Rev. 3.00 Jan. 18, 2008 Page 179 of 1458
REJ09B0033-0300
4.3.2
TLB Indexing
The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16
to 12 and ASID bits 4 to 0 in PTEH are used as the index number regardless of the page size. The
index number can be generated in two different ways depending on the setting of the IX bit in
MMUCR.
1. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate a 5-bit index
number
2. When IX = 0, VPN bits 16 to 12 alone are used as the index number
The first method is used to prevent lowered TLB efficiency that results when multiple processes
run simultaneously in the same virtual address space (multiple virtual memory) and a specific
entry is selected by indexing of each process. In single virtual memory mode (MMUCR.SV = 1),
IX bit should be set to 0. Figures 4.8 and 4.9 show the indexing schemes.
31
16
11
12
17
0
31
0
PTEH register
Virtual address
VPN
0
ASID
7
10
Index
ASID(4 to 0)
Exclusive-OR
Way 0 to 3
VPN(31 to 17)
VPN(11 to 10)
ASID(7 to 0)
V
0
31
Address Array
Data Array
PPN(28 to 10) PR(1 to 0) SZ
C
D
SH
Figure 4.8 TLB Indexing (IX = 1)



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