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SH7721 Datasheet(PDF) 239 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 239 Page - Renesas Technology Corp

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Section 4 Memory Management Unit (MMU)
Rev. 3.00 Jan. 18, 2008 Page 177 of 1458
REJ09B0033-0300
4.3
TLB Functions
4.3.1
Configuration of the TLB
The TLB caches address translation table information located in the external memory. The address
translation table stores the virtual page number and the corresponding physical number, the
address space identifier, and the control information for the page, which is the unit of address
translation. Figure 4.6 shows the overall TLB configuration. The TLB is 4-way set associative
with 128 entries. There are 32 entries for each way. Figure 4.7 shows the configuration of virtual
addresses and TLB entries.
Entry 1
Address array
Data array
Entry 0
Entry 1
Entry 31
Way 0 to 3
Way 0 to 3
VPN(11 to 10)
VPN(31 to 17)
ASID(7 to 0)
V
Entry 0
Entry 31
PPN(28 to 10)PR(1 to 0) SZ
C
D SH
Figure 4.6 Overall Configuration of the TLB



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