SH7721 datasheet(246/1524 Pages) RENESAS

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Section 4 Memory Management Unit (MMU)

Rev. 3.00 Jan. 18, 2008 Page 184 of 1458

REJ09B0033-0300

4.4.2

MMU Software Management

There are three kinds of MMU software management, as follows.

1. MMU register setting

MMUCR setting, in particular, should be performed in areas P1 and P2 for which address

translation is not performed. Also, since SV and IX bit changes constitute address translation

system changes, in this case, TLB flushing should be performed by simultaneously writing 1 to

the TF bit also. Since MMU exceptions are not generated in the MMU disabled state with the

AT bit cleared to 0, use in the disabled state must be avoided with software that does not use

the MMU.

2. TLB entry recording, deletion, and reading

TLB entry recording can be done in two ways by using the LDTLB instruction, or by writing

directly to the memory-mapped TLB. For TLB entry deletion and reading, the memory

allocation TLB can be accessed. See section 4.4.3, MMU Instruction (LDTLB), for details of

the LDTLB instruction, and section 4.6, Memory-Mapped TLB, for details of the memory-

mapped TLB.

3. MMU exception processing

When an MMU exception is generated, it is handled on the basis of information set from the

hardware side. See section 4.5, MMU Exceptions, for details.

When single virtual memory mode is used, it is possible to create a state in which physical

memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to

specify recording of all TLB entries. This strengthens inter-process memory protection, and

enables special access levels to be created in the privileged mode only.

Recording a 1- or 4- kbyte page TLB entry may result in a synonym problem. See section 4.4.4,

Avoiding Synonym Problems.

4.4.3

MMU Instruction (LDTLB)

The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is

0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR

to the value specified by PTEH and PTEL, using VPN bits 16 to 12 specified in PTEH as the

index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16 to 12 specified in

PTEH and ASID bits 4 to 0 in PTEH are used as the index number.

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