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3850 Datasheet(PDF) 39 Page - Renesas Technology Corp |
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3850 Datasheet(HTML) 39 Page - Renesas Technology Corp |
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39 / 261 page ![]() 1-24 3850/3851 Group User’s Manual HARDWARE Fig. 21 Structure of serial I/O control registers b7 b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) Serial I/O status register Serial I/O control register b0 b0 BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY output enable bit (SRDY) 0: P27 pin operates as ordinary I/O pin 1: P27 pin operates as S RDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P24 to P27 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P24 to P27 operate as serial I/O pins) b7 UART control register Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P25/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) b0 (SIOSTS : address 0019 16) (SIOCON : address 001A 16) (UARTCON : address 001B 16) FUNCTIONAL DESCRIPTION |
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