3850 datasheet(13/261 Pages) RENESAS

13 / 261 page

3850/3851 Group User’s Manual

List of figures

Fig. 2.4.27 Transmission process of upper data ..................................................................... 2-79

Fig. 2.4.28 Reception of STOP condition ................................................................................. 2-80

Fig. 2.5.1 Memory map of registers relavant to PWM ........................................................... 2-85

Fig. 2.5.2 Structure of PWM control register ........................................................................... 2-85

Fig. 2.5.3 Structure of PWM prescaler ..................................................................................... 2-86

Fig. 2.5.4 Structure of PWM register ........................................................................................ 2-86

Fig. 2.5.5 Connection diagram ................................................................................................... 2-87

Fig. 2.5.6 PWM output timing ..................................................................................................... 2-87

Fig. 2.5.7 Setting of related registers ....................................................................................... 2-88

Fig. 2.5.8 PWM output ................................................................................................................ 2-88

Fig. 2.5.9 Control procedure ....................................................................................................... 2-89

Fig. 2.6.1 Memory map of registers relevant to A-D converter ............................................ 2-90

Fig. 2.6.2 Structure of A-D control register .............................................................................. 2-90

Fig. 2.6.3 Structure of A-D conversion register (high-order) ................................................. 2-91

Fig. 2.6.4 Structure of A-D conversion register (low-order) ................................................... 2-91

Fig. 2.6.5 Structure of Interrupt request register 2 ................................................................. 2-92

Fig. 2.6.6 Structure of Interrupt control register 2 .................................................................. 2-92

Fig. 2.6.7 Connection diagram ................................................................................................... 2-93

Fig. 2.6.8 Relevant registers setting ......................................................................................... 2-93

Fig. 2.6.9 Control procedure for 8-bit read .............................................................................. 2-94

Fig. 2.6.10 Control procedure for 10-bit read .......................................................................... 2-94

Fig. 2.7.1 Example of poweron reset circuit ............................................................................ 2-96

Fig. 2.7.2 RAM backup system .................................................................................................. 2-96

CHAPTER 3 APPENDIX

Fig. 3.1.1 Circuit for measuring output switching characteristics (1) ..................................... 3-9

Fig. 3.1.2 Circuit for measuring output switching characteristics (2) ..................................... 3-9

Fig. 3.1.3 Timing chart ................................................................................................................ 3-10

Fig. 3.1.4 Timing diagram of multi-master I2C-BUS ................................................................ 3-11

Fig. 3.2.1 Power source current characteristic examples (f(XIN) = 8MHz, in high-speed mode)

..................................................................................................................................... 3-12

Fig. 3.2.2 Power source current characteristic examples (f(XIN) = 8MHz, in middle-speed mode)

..................................................................................................................................... 3-12

Fig. 3.2.3 Power source current characteristic examples (f(XIN) = 4MHz, in high-speed mode)

..................................................................................................................................... 3-13

Fig. 3.2.4 Power source current characteristic examples (f(XIN) = 4MHz, in middle-speed mode)

..................................................................................................................................... 3-13

Fig. 3.2.5 Power source current characteristic examples (f(XCIN) = 32KHz, in low-speed mode)

..................................................................................................................................... 3-14

Fig. 3.2.6 Standard characteristic examples of CMOS output port at P-channel drive ..... 3-15

Fig. 3.2.7 Standard characteristic examples of CMOS output port at N-channel drive ..... 3-15

Fig. 3.2.8 Standard characteristic examples of N-channel open-drain output port at N-channel

drive ............................................................................................................................. 3-16

Fig. 3.2.9 Standard characteristic examples of CMOS large current output port at N-channel

drive ............................................................................................................................. 3-16

Fig. 3.2.10 A-D conversion standard characteristics............................................................... 3-17

Fig. 3.3.1 Sequence of switch the detection edge .................................................................. 3-18

Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-18

Fig. 3.3.3 Sequence of setting serial I/O control register again ........................................... 3-20

Fig. 3.3.4 Ceramic resonator circuit .......................................................................................... 3-26

Fig. 3.3.5 Initialization of processor status register ................................................................ 3-27

Fig. 3.3.6 Sequence of PLP instruction execution .................................................................. 3-27

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