3850 datasheet(49/261 Pages) RENESAS

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3850/3851 Group User’s Manual

HARDWARE

Example of Master Transmission

An example of master transmission in the standard clock mode, at

the SCL frequency of 100 kHz and in the ACK return mode is

shown below.

Set a slave address in the high-order 7 bits of the I2C address

Set the ACK return mode and SCL = 100 kHz by setting “8516”

in the I2C clock control register (address 002F16).

Set “0016” in the I2C status register (address 002D16) so that

transmission/reception mode can become initializing condition.

Set a communication enable status by setting “0816” in the I2C

control register (address 002E16).

Confirm the bus free condition by the BB flag of the I2C status

Set the address data of the destination of transmission in the

high-order 7 bits of the I2C data shift register (address 002B16)

and set “0” in the least significant bit.

Set “F016” in the I2C status register (address 002D16) to gener-

ate a START condition. At this time, an SCL for 1 byte and an

ACK clock automatically occur.

Set transmit data in the I2C data shift register (address 002B16).

At this time, an SCL and an ACK clock automatically occur.

When transmitting control data of more than 1 byte, repeat step

Set “D016” in the I2C status register (address 002D16) to gener-

ate a STOP condition if ACK is not retur ned from slave

reception side or transmission ends.

Example of Slave Reception

An example of slave reception in the high-speed clock mode, at

the SCL frequency of 400 kHz, in the ACK non-return mode and

using the addressing format is shown below.

Set a slave address in the high-order 7 bits of the I2C address

Set the no ACK clock mode and SCL = 400 kHz by setting

“6516” in the I2C clock control register (address 002F16).

Set “0016” in the I2C status register (address 002D16) so that

transmission/reception mode can become initializing condition.

Set a communication enable status by setting “0816” in the I2C

control register (address 002E16).

When a START condition is received, an address comparison is

performed.

•When all transmitted addresses are “0” (general call):

AD0 of the I2C status register (address 002D16) is set to “1”

and an interrupt request signal occurs.

• When the transmitted addresses agree with the address set

in :

ASS of the I2C status register (address 002D16) is set to “1”

and an interrupt request signal occurs.

• In the cases other than the above AD0 and AAS of the I2C sta-

tus register (address 002D16) are set to “0” and no interrupt

request signal occurs.

Set dummy data in the I2C data shift register (address 002B16).

When receiving control data of more than 1 byte, repeat step .

When a STOP condition is detected, the communication ends.

FUNCTIONAL DESCRIPTION

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