3850 datasheet(14/261 Pages) RENESAS

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3850/3851 Group User’s Manual

List of figures

Fig. 3.3.7 Stack memory contents after PHP instruction execution ..................................... 3-27

Fig. 3.3.8 Interrupt routine .......................................................................................................... 3-28

Fig. 3.3.9 Status flag at decimal calculations .......................................................................... 3-28

Fig. 3.3.10 Programming and testing of One Time PROM version ...................................... 3-29

Fig. 3.4.1 Selection of packages ............................................................................................... 3-32

Fig. 3.4.2 Wiring for the RESET pin ......................................................................................... 3-32

Fig. 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-33

Fig. 3.4.4 Wiring for CNVss pin ............................................................................................... 3-33

Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM and the EPROM version ......... 3-34

Fig. 3.4.6 Bypass capacitor across the Vss line and the Vcc line ....................................... 3-34

Fig. 3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-35

Fig. 3.4.8 Wiring for a large current signal line ...................................................................... 3-35

Fig. 3.4.9 Wiring of RESET pin ................................................................................................. 3-36

Fig. 3.4.10 Vss pattern on the underside of an oscillator ..................................................... 3-36

Fig. 3.4.11 Setup for I/O ports ................................................................................................... 3-37

Fig. 3.4.12 Watchdog timer by software ................................................................................... 3-38

Fig. 3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4) ....................................................................... 3-39

Fig. 3.5.2 Structure of Port Pi direction register(i=0, 1, 2, 3, 4) .......................................... 3-39

Fig. 3.5.3 Structure of Transmit/Receive buffer register ........................................................ 3-40

Fig. 3.5.4 Structure of Serial I/O status register ..................................................................... 3-40

Fig. 3.5.5 Structure of Serial I/O control register .................................................................... 3-41

Fig. 3.5.6 Structure of UART control register .......................................................................... 3-41

Fig. 3.5.7 Structure of Baud rate generator ............................................................................. 3-42

Fig. 3.5.8 Structure of PWM control register ........................................................................... 3-42

Fig. 3.5.9 Structure of PWM prescaler ..................................................................................... 3-43

Fig. 3.5.10 Structure of PWM register ...................................................................................... 3-43

Fig. 3.5.11 Structure of Prescaler 12, Prescaler X, Prescaler Y .......................................... 3-44

Fig. 3.5.12 Structure of Timer 1 ................................................................................................ 3-44

Fig. 3.5.13 Structure of Timer 2, Timer X, Timer Y ............................................................... 3-45

Fig. 3.5.14 Structure of timer count source selection register .............................................. 3-45

Fig. 3.5.15 Structure of Timer XY mode register .................................................................... 3-46

Fig. 3.5.16 Structure of I2C data shift register ......................................................................... 3-47

Fig. 3.5.17 Structure of I2C address register ........................................................................... 3-47

Fig. 3.5.18 Structure of I2C status register .............................................................................. 3-48

Fig. 3.5.19 Structure of I2C control register ............................................................................. 3-48

Fig. 3.5.20 Structure of I2C clock control register ................................................................... 3-49

Fig. 3.5.21 Structure of I2C START/STOP condition control register ................................... 3-50

Fig. 3.5.22 Structure of A-D control register ............................................................................ 3-50

Fig. 3.5.23 Structure of A-D conversion register(low-order) .................................................. 3-51

Fig. 3.5.24 Structure of A-D conversion register (high-order) ............................................... 3-51

Fig. 3.5.25 Structure of MISRG ................................................................................................. 3-52

Fig. 3.5.26 Structure of Watchdog timer control register ....................................................... 3-52

Fig. 3.5.27 Structure of Interrupt edge selection register ...................................................... 3-53

Fig. 3.5.28 Structure of CPU mode register ............................................................................ 3-53

Fig. 3.5.29 Structure of Interrupt request register 1 ............................................................... 3-54

Fig. 3.5.30 Structure of Interrupt request register 2 ............................................................... 3-54

Fig. 3.5.31 Structure of Interrupt control register 1 ................................................................ 3-55

Fig. 3.5.32 Structure of Interrupt control register 2 ................................................................ 3-55

Fig. 3.13.1 M38513M4-XXXFP/SP pin configuration ............................................................... 3-91

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