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3850/3851 Group User’s Manual

HARDWARE

1-49

A-D Converter

A-D conversion is started by setting AD conversion completion bit

to “0”. During A-D conversion, internal operations are performed

as follows.

1. After the start of A-D conversion, A-D conversion register

goes to “0016”.

2. The highest-order bit of A-D conversion register is set to

“1”. and the comparison voltage Vref is input to the

comparator. Then, Vref is compared with analog input voltage

VIN.

3. As a result of comparison, when Vref < VIN, the highest-

order bit of A-D conversion register be- comes “1.” When

Vref > VIN, the highest-order bit becomes “0.”

By repeating the above operations up to the lowest-order bit of the

A-D conversion register, an analog value converts into a digital

value.

A-D conversion completes at 61 clock cycles (15.25

µs at f(XIN) =

8.0 MHz) after it is started, and the result of the conversion is

stored into the A-D conversion register.

Concurrently with the completion of A-D conversion, the A-D con-

version completion bit is set to “1” and an A-D conversion interrupt

request occurs, so that the AD conversion interrupt request bit is

set to “1”.

Relative formula for a reference voltage VREF of A-D converter and Vref

When n = 0

Vref = 0

When n = 1 to 1023

Vref =

! n

n : the value of A-D converter (decimal numeral)

VREF

1024

V1–V10: A result of the first to tenth comparison

Table 14 Change of A-D conversion register during A-D conversion

At start of conversion

First comparison

Second comparison

Third comparison

After completion of

tenth comparison

000

VREF

±±

A result of A-D conversion

V 1

V 1 V 2

Change of A-D conversion register

Value of comparison voltage (Vref)

V 9 V10

1024

VREF

±±

± •••

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FUNCTIONAL DESCRIPTION SUPPLEMENT

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