7477 datasheet(131/354 Pages) RENESAS

131 / 354 page

HARDWARE

1-114

7470/7471/7477/7478 GROUP USER’S MANUAL

1.13 Serial I/O

(2) Clock asynchronous Serial I/O

In case of the clock asynchronous Serial I/O (UART), the transmit operation of the transmit side and

the receive operation of the receive side are simultaneously executed by unifying the baud rate and

the transfer data format between both transmit side and receive side.

Figure 1.13B.6 shows a UART block diagram.

Fig. 1.13B.6 UART block diagram

1/4

P14

P15

P16

TXD

SCLK

RXD

1/16

ST/SP/PA occur

Receive enable bit

(RE)

Serial I/O enable bit(SIOE)

Address 00E016

Receive buffer register

Receive shift register

Serial I/O control register

Address 00E216

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Clock control circuit

Serial I/O synchronous clock selection bit

(SCS)

Transmit shift completion flag (TSC)

Transmit interrupt request (TI)

Transmit buffer empty flag (TBE)

Serial I/O status register Address 00E116

Data bus

Address 00E016

Address 00E416

Transmit buffer register

Transmit shift register

Transmit interrupt source

selection bit (TIC)

Dividing ratio 1/(n+1)

Baud rate generator

BRG count source

selection bit (CSS)

Transmit enable bit (TE)

Data bus

Character length

selection bit (CHAS)

ST detected

7 bits

8 bits

SP detected

Character length

selection bit (CHAS)

UART control register

Address 00E316

XCIN

V: The 7477 group is not provided with the X

pin.

XIN

CIN

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