7477 datasheet(132/354 Pages) RENESAS

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HARDWARE

1-115

7470/7471/7477/7478 GROUP USER’S MANUAL

1.13 Serial I/O

Input clock oscillation frequency to SCLK pin

2 Synchronous clock

The following can be selected as a synchronous clock by bit 1 of the Serial I/O control register

(SIOCON: address 00E216).

q “0” : Baud rate generator (BRG) output divided by 16

q “1” : External clock input from the SCLK pin divided by 16

The BRG output is set by the baud rate generator (BRG: address 00E416), which is an 8-bit

counter dedicated to the Serial I/O. As an input clock to the BRG, f(XIN)/4 (at “0”), f(XIN)/16 (at

“1”) can be selected by bit 0 of the Serial I/O control register. In the 7478 Group, f(XCIN)/4 (at “0”),

f(XCIN)/16 (at “1”), can be also selected.

Precaution on internal clock selection

In the UART, when the internal clock is selected as a synchronous clock, the P16/SCLK pin can

be used as port P16.

Notes on external clock selection

q Set the “H” and “L” widths (TWH, TWL) of the pulse used as the external clock source to TWH,

TWL [s]

> 2/(f(XIN) [Hz]). For example, when f(XIN) = 8 MHz, use a clock of 2 MHz or less (duty

ratio 50 %).

2 Data transfer speed (Baud rate)

In the UART, the expression for calculating a data transfer speed (baud rate), which is the frequency

of the synchronous clock is shown below.

q When the internal clock is selected (using the BRG)

Baud rate [bps] =

V1 Division ratio : Select “4” or “16” by the BRG count source selection bit.

V2 BRG set value : 0 – 255 (0016 – FF16)

V3 In the 7478 Group, f(XCIN) can be also used.

q When the external clock is selected

Baud rate [bps] =

f(XIN)

Division ratio

V1 ! (BRG set valueV2 + 1) ! 16

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