AD9239 datasheet(19/40 Pages) AD

19 / 40 page

AD9239

Rev. 0 | Page 19 of

cation.

THEORY OF OPERATION

The AD9239 architecture consists of a differential input buffer,

front-end sample-and-hold amplifier (SHA) followed by a

pipelined switched capacitor ADC. The quantized outputs from

each stage are combined into a final 12-bit result in the digital

correction logic. The pipelined architecture permits the first

stage to operate on a new input sample, while the remaining

stages operate on preceding samples. Sampling occurs on the

rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor DAC

and interstage residue amplifier (for example, a multiplying

digital-to-analog converter (MDAC)). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The input stage contains a differential SHA that can be ac- or

dc-coupled in differential or single-ended mode. The output of

the pipeline ADC is put into its final serial format by the data

serializer, encoder, and CML drivers block. The data rate multiplier

creates the clock used to output the high speed serial data at the

CML outputs.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9239 is a differential buffer. This

input is optimized to provide superior wideband performance

and requires that the analog inputs be driven differentially. SNR

and SINAD performance degrades if the analog input is driven

with a single-ended signal.

For best dynamic performance, the source impedances driving

VIN + x and VIN − x should be matched such that common-

mode settling errors are symmetrical. These errors are reduced

by the common-mode rejection of the ADC. A small resistor in

series with each input can help reduce the peak transient current

injected from the output stage of the driving source.

In addition, low-Q inductors or ferrite beads can be placed on

each leg of the input to reduce high differential capacitance at

the analog inputs and therefore achieve the maximum bandwidth

of the ADC. Such use of low-Q inductors or ferrite beads is

required when driving the converter front end at high intermediate

frequency (IF). Either a shunt capacitor or two single-ended capac-

itors can be placed on the inputs to provide a matching passive

network. This ultimately creates a low-pass filter at the input to

limit unwanted broadband noise. See the AN-827 Application Note

and the Analog Dialogue article “Transformer-Coupled Front-End

for Wideband A/D Converters” (Volume 39, April 2005) for

more information on this subject. In general, the precise values

depend on the appli

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. In the case of the

AD9239, the default input span is 1.25 V p-p. To configure the

ADC for a different input span, see Register 18. For the best

performance, an input span of 1.25 V p-p or greater should be

used (see Table 14 for details).

Differential Input Configurations

There are several ways to drive the AD9239 either actively or

passively; in either case, optimum performance is achieved by

driving the analog input differentially. For example, using the

ADA4937 differential amplifier to drive the AD9239 provides

excellent performance and a flexible interface to the ADC (see

Figure 45 and Figure 46) for baseband and second Nyquist

(~100 MHz IF) applications. In either application, 1% resistors

should be used for good gain matching. It should also be noted

that the dc-coupled configuration will show some degradation

in spurious performance. For further reference, consult the

ADA4937 data sheet.

SIGNAL

GENERATOR

+VS

–VS

3.3V

205Ω

200Ω

10kΩ

62Ω

10kΩ

27Ω

0.1µF

1.25V p-p

ADA4937

G = UNITY

VIN + x

VIN – x

OPTIONAL C

33Ω

24Ω

0.1µF

AVDD

DRVDD

1.8V

AD9239

ADC INPUT

IMPEDANCE

1.65V

VOCM

Figure 45. Differential Amplifier Configuration for AC-Coupled Baseband Applications

SIGNAL

GENERATOR

+VS

–VS

3.3V

205Ω

200Ω

62Ω

27Ω

0.1µF

1.25V p-p

ADA4937

G = UNITY

VIN + x

VIN – x

OPTIONAL C

33Ω

24Ω

AVDD

DRVDD

1.8V

AD9239

ADC INPUT

IMPEDANCE

VOCM

VCMx

1.4V

Figure 46. Differential Amplifier Configuration for DC-Coupled Baseband Applications

AD9239 Datasheet(PDF) 19 Page - Analog Devices

AD9239 Datasheet(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL