AD9239 datasheet(34/40 Pages) AD

34 / 40 page

AD9239

Rev. 0 | Page 34 of

Table 14. Memory Map Register

Addr.

(Hex)

Name

(MSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Bit 0

Default

Value

(Hex)

Default

Notes/

Comments

Chip Configuration Registers

chip_port_

config (local,

master)

SDO active

(not

required,

ignored if

not used)

LSB

first

Soft

reset

16 bit

address

(default

mode for

ADCs)

0x18

chip_id

(global)

8-bit Chip ID Bits[2:0]

0x0B – AD9239 – 12-bit quad

Read

only

chip_grade

(global)

Speed grade

010 = 170

100 = 210

101 = 250

Read

only

Device Index and Transfer Registers

device_

index_A

(global)

ADC A

ADC B

ADC C

ADC D

0x0F

Bits are set

to determine

which device

on chip

receives the

next write

command.

The default

is all devices

on chip.

device_

update (local,

master)

transfer

1 = on

0 = off

(default)

0x00

Synchro-

nously

transfers

data from

the master

shift register

to the slave.

ADC Functions Registers

modes

(local)

External

PDWN

function

00 = full

PDWN

(default)

01 =

standby

00 = chip run

(default)

01 = full power-down

10 = standby

11 = reset

0x00

Determines

various ge-

neric modes

of chip

operation.

Clock

(global)

Duty

cycle

stabilize

1 = on

(default)

0 = off

0x01

Turns the

internal

duty cycle

stabilizer

on and off.

test_io

(local)

Reset PN

long gen

1 = on

0 = off

(default)

Reset PN

short gen

1 = on

0 = off

(default)

Flex output test mode

0000 = off (normal operation)

0001 = midscale short

0010 = +FS short

0011 = −FS short

0100 = checkerboard output

0101 = PN 23 sequence

0110 = PN 9 sequence

0111 = one/zero word toggle

0x00

When set,

the test data

is placed on

the output

pins in place

of normal

data.

test_bist

(local)

BIST init

1 = on

0 = off

(default)

BIST

enable

1 = on

0 = off

(default)

0x00

When Bit 0

is set, the

built-in self-

test function

is initiated.

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