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AD9239

Rev. 0 | Page 23 of

Digital Start-Up Sequence

A 100 Ω differential termination resistor should be placed at each

receiver input to result in a nominal 800 mV p-p swing at the

receiver. Alternatively, single-ended 50 Ω termination can be

used. When single-ended termination is used, the termination

voltage should be DRVDD/2; otherwise, ac coupling capacitors

can be used to terminate to any single-ended voltage.

The output digital data from the AD9239 is coded and packetized,

which requires the device to have a certain start-up sequence.

The following steps should be initialized by the user to capture

coherent data at the receiving logic.

Initialize a soft reset via Bit 5 of Register 0 (see Table 14).

The AD9239 digital outputs can interface with custom application-

specific integrated circuits (ASICs) and field-programmable gate

array (FPGA) receivers, providing superior switching performance

in noisy environments. Single point-to-point net topologies are

recommended with a single differential 100 Ω termination resistor

placed as close to the receiver logic as possible. The common mode

of the digital output automatically biases itself to half the supply

of the receiver (that is, the common-mode voltage is 0.9 V for a

receiver supply of 1.8 V) if dc-coupled connecting is used. For

receiver logic that is not within the bounds of the DRVDD supply,

an ac-coupled connection should be used. Simply place a 0.1 μF

capacitor on each output pin and derive a 100 Ω differential

termination close to the receiver side.

All PGMx pins are automatically initialized as sync pins by

default. These pins can be used to lock the FPGA timing

and data capture during initial startup. These pins are

respective to each channel (PGM3 = Channel A).

Each sync pin is held low until its respective PGMx pin

receives a high signal input from the receiver, during which

time the ADC outputs a training pattern.

The training pattern defaults to the values implemented by

the user in Register 19 through Register 20.

When the receiver finds the frame boundary, the sync

identification is deasserted high via the sync pin or via a

SPI write. The ADC outputs the valid data on the next packet

boundary. The time necessary for sync establishment is highly

dependent on the receiver logic processing. Refer to the

Switching Specifications section; the switching timing is

directly related to the ADC channel.

If there is no far-end receiver termination or there is poor

differential trace routing, timing errors may result. To avoid

such timing errors, it is recommended that the trace length be

less than 6 inches and that the differential output traces be close

together and at equal lengths.

Once steady state operation for the device has occurred,

these pins can each be assigned to be a standby option by

using Register 53 (see Table 14). All other pins act as

universal sync pins.

100Ω

DIFFERENTIAL

TRACE PAIR

DOUT + x

DRVDD

DOUT – x

VCM = DRVDD/2

OUTPUT SWING = 400mV p-p

RECEIVER

To minimize skew and time misalignment between each

channel of the digital outputs, the following actions should be

taken to ensure that each channel data packet is within ±1 clock

cycle of its specified switching time. For some receiver logic,

this is not required.

Figure 61. DC-Coupled Digital Output Termination Example

Full power-down through external PDWN pin.

Chip reset via external RESET pin.

100Ω

DIFFERENTIAL

TRACE PAIR

DOUT + x

DRVDD

VRXCM

DOUT – x

VCM = Rx VCM

OUTPUT SWING = 400mV p-p

0.1µF

RECEIVER

Power back up by releasing external PDWN pin.

Digital Outputs and Timing

The AD9239 has differential digital outputs that power up on

default. The driver current is derived on chip and sets the output

current at each output equal to a nominal 8 mA. Each output

presents a 100 Ω dynamic internal termination to reduce unwanted

reflections

Figure 62. AC-Coupled Digital Output Termination Example

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