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ADP5501 Datasheet(PDF) 3 Page - Analog Devices

Part # ADP5501
Description  Programmable Current Backlight Driver with Ambient Light Sensor Input
PDF  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADP5501 Datasheet(HTML) 3 Page - Analog Devices

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ADP5501
Rev. 0 | Page 3 of 28
SPECIFICATIONS
VBAT = 2.7 V to 5.5 V, TJ = −400C to +1250C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions1
Min
Typ
Max
Unit
SUPPLY VOLTAGE
VBAT Input Voltage Range
VBAT
2.7
5.5
V
VDDIO Input Voltage Range
VIO
1.8
3.32
V
Undervoltage Lockout Threshold
UVLOVBAT
VBAT falling
1.7
2.1
V
UVLOVBAT
VBAT rising
2.4
2.7
V
UVLOVDDIO
VDDIO falling
1.1
1.3
V
UVLOVDDIO
VDDIO rising
1.4
V
SW Leakage
SWLEAKAGE
2.7 V ≤ VBAT ≤ 5.5 V
0.1
1
μA
SUPPLY CURRENT
Shutdown Current3
ISD
VDDIO = 0 V
0.1
1
μA
Standby Current4
ISTNBY
1.8 V ≤ VDDIO ≤ 3.3 V2,
STNBY = 0
25
45
μA
BACKLIGHT LED DRIVER (SW, BST)
Current Limit (Peak Inductor Current)
450
600
750
mA
On Resistance
200
200
400
mΩ
Overvoltage Threshold
24.5
27
29.5
V
Boost Startup Time
1
mS
BACKLIGHT LED CURRENT SINK (BL_SNK)
Full-Scale Current Sink
Backlight code = 0x7F,
bias = 0.65 V
26
30
32
mA
Backlight Current Ramp Rate
Fade timers disabled
0.3
mA/ms
AMBIENT LIGHT SENSOR (CMP_IN)
Full-Scale Current
BLFULLSCALE
0.7
1
1.2
mA
INPUT LOGIC LEVELS (SCL, SDA, RST)
Logic Low Input Voltage
VIL
1.8 V ≤ VDDIO ≤ 3.3 V2
0.3 × VDDIO
V
Logic High Input Voltage
VIH
1.8 V ≤ VDDIO ≤ 3.3 V2
0.7 × VDDIO
V
Input Leakage Current
VI-LEAKAGE
1.8 V ≤ VDDIO ≤ 3.3 V2
0.1
1
μA
INPUT LOGIC DEBOUNCE (RST)
VIL-DBNC
50
75
100
μs
OPEN-DRAIN OUTPUT LOGIC LEVELS (INT, SDA)
Logic Low Output Voltage
VOL
ISINK = 1mA
0.4
V
Logic High Leakage Current
VOH-LEAKAGE
1.8 V ≤ VDDIO ≤ 3.3 V2
0.1
1
μA
AUX LED CURRENT SINKs (ILED, C3, R3)
Leakage
LEDLEAKAGE
Sink disabled
0.1
1
μA
Full-Scale Current Sink
LEDFULLSCALE
Applied pin voltage = 1 V
10.5
14
16.5
mA
THERMAL SHUTDOWN
Thermal Shutdown Threshold
TS
TJ rising
150
°C
Thermal Shutdown Hysteresis
TSHYS
TJ falling
10
°C
I2C TIMING SPECIFICATIONS
Delay from Reset Deassertion to I2C Access
60
μs
SCL Clock Frequency
fSCL
400
kHz
SCL High Time
tHIGH
0.6
μs
SCL Low Time
tLOW
1.3
μs
Data Setup Time
tSU, DAT
100
ns
Data Hold Time
tHD, DAT
0
0.9
μs
Setup Time for Repeated Start
tSU, STA
0.6
μs



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