HC210W datasheet(52/228 Pages) ALTERA

52 / 228 page

4–10

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

Receiver differential input

discrete resistor (external to

HardCopy II devices)

—

100

110

Notes to Table 4–12:

(1)

Like Stratix II devices, LVPECL is supported by the top and bottom clock input differential buffers, and by the PLL

clock output and feedback pins.

(2)

The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO.

The PLL clock output and feedback differential buffers are powered by

VCC_PLLOUT. For differential clock output

and feedback operation, connect

VCC_PLLOUT to 3.3 V.

Table 4–12. LVPECL Specifications (Part 2 of 2)

Note (1)

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Unit

Table 4–13. HyperTransport Technology Specifications

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Unit

VCCIO

I/O supply voltage for I/O

banks that support

high-speed IOEs (1), (2)

—

2.375

2.5

2.625

Output and feedback pins in

PLL banks 9, 10, 11, and 12

—

3.135

3.3

3.465

VID (peak-

to-peak)

Input differential voltage

swing (single-ended)

—

300

600

900

VICM

Input common mode voltage

—

385

600

845

VOD

Output differential voltage

(single-ended)

RL = 100

400

600

820

ΔVOD

Change in VOD between high

and low

RL = 100

——

VOCM

Output common mode

voltage

RL = 100

440

600

780

ΔV

OCM

Change in VOCM between

high and low

RL = 100

——

Receiver differential input

discrete resistor (external to

HardCopy II devices)

—

100

110

Notes to Table 4–13:

(1)

For information on which I/O banks support high-speed IOEs, refer to the Description, Architecture, and Features

chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook.

(2)

The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO.

The PLL clock output and feedback differential buffers are powered by

VCC_PLLOUT. For differential clock output

and feedback operation, connect

VCC_PLLOUT to 3.3 V.

HC210W Datasheet(PDF) 52 Page - Altera Corporation

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