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HC210W Datasheet(PDF) 72 Page - Altera Corporation |
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HC210W Datasheet(HTML) 72 Page - Altera Corporation |
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72 / 228 page  4–30 Altera Corporation September 2008 HardCopy Series Handbook, Volume 1 2.5-V LVTTL / LVCMOS 4 mA 136 136 136 136 136 136 136 MHz 8 mA 230 230 230 230 230 230 230 MHz 12 mA 370 370 370 370 370 370 370 MHz 16 mA (3) 405 — — — — 405 405 MHz 1.8-V LVTTL / LVCMOS 2 mA 7777 77 77 77 7777 MHz 4 mA 150 150 150 150 150 150 150 MHz 6 mA 180 180 180 180 180 180 180 MHz 8 mA 200 200 200 200 200 200 200 MHz 10 mA 250 — — — — 250 250 MHz 12 mA (3) 290 — — — — 290 290 MHz 1.5-V LVTTL / LVCMOS 2 mA 6060 60 60 60 6060 MHz 4 mA 110 110 110 110 110 110 110 MHz 6 mA 150 — — — — 150 150 MHz 8mA (3) 190 — — — — 190 190 MHz SSTL2 class I 8 mA 210 — — — — 210 210 MHz 12 mA (3) 280 — — — — 280 280 MHz SSTL2 class II 16 mA 245 — — — — 245 245 MHz 20 mA 245 — — — — 245 245 MHz 24 mA (3) 280 — — — — 280 280 MHz SSTL18 class I 4 mA 105 — — — — 105 105 MHz 6 mA 175 — — — — 175 175 MHz 8 mA 210 — — — — 210 210 MHz 10 mA 220 — — — — 220 220 MHz 12 mA (3) 230 — — — — 230 230 MHz SSTL18 class II 8 mA 140 — — — — 140 140 MHz 16 mA 220 — — — — 220 220 MHz 18 mA 220 — — — — 220 220 MHz 20 mA (3) 350 — — — — 350 350 MHz Table 4–36. HardCopy II Maximum Output Clock Rate for HC210W Devices Notes (1), (6) (Part 2 of 4) I/O Standard Drive Strength Memory Interface IOEs High Speed IOEs General Purpose IOEs CLK [0, 2, 8, 10] (2) CLK [4..7, 12..15] PLL_OUT Unit Bottom Column Right Row |
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