HC210W datasheet(18/228 Pages) ALTERA

18 / 228 page

2–10

Altera Corporation

Preliminary

September 2008

HardCopy Series Handbook, Volume 1

Table 2–4. HardCopy II Embedded Memory Features

(Part 1 of 2) Notes (1), (2), (3)

Feature

M4K Blocks

M-RAM Blocks

Maximum performance (1), (4)

350 MHz

Total RAM bits (including parity bits)

4,608

589,824

Configurations

4K × 1

2K × 2

1K × 4

512 × 8

512 × 9

256 × 16

256 × 18

128 × 32

128 × 36

64K × 8

64K × 9

32K × 16

32K × 18

16K × 32

16K × 36

8K × 64

8K × 72

4K × 128

4K × 144

Parity bits

Byte enable

Pack mode

Address clock enable

Single-port memory

Simple dual-port memory

True dual-port memory

Embedded shift register

ROM

FIFO buffer

Simple dual-port mixed width support

True dual-port mixed width support

Memory initialization file (.mif)

Not supported, except in ROM

mode

Not supported

Mixed-clock mode

Power-up condition (2)

Outputs unknown

Output registers only

Same-port read-during-write

New data available at positive clock

edge

New data available at positive clock

edge

Mixed-port read-during-write

Outputs set to unknown or old data Unknown output

HC210W Datasheet(PDF) 18 Page - Altera Corporation

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