HC210W datasheet(31/228 Pages) ALTERA

31 / 228 page

Altera Corporation

2–23

September 2008

Preliminary

I/O Structure and Features

■

SSTL-2 class I and II

■

SSTL-18 class I and II

■

1.8-V HSTL class I and II

■

1.5-V HSTL class I and II

The memory interface DQS,

CLK, and PLL_FB input pins and the

PLL_OUT output pins support the following I/O standards:

■

LVTTL/LVCMOS

■

SSTL-2 class I and II

■

SSTL-18 class I and II

■

1.8-V HSTL class I and II

■

1.5-V HSTL class I and II

■

Differential SSTL-2 class I and II

■

Differential SSTL-18 class I and II

■

1.8-V differential HSTL class I and II

■

1.5-V differential HSTL class I and II

■

LVDS (not supported on DQS pins)

■

HyperTransport technology (not supported on DQS pins)

■

LVPECL on input clocks and

PLL_OUT only (not supported on DQS

pins)

Pseudo-differential HSTL and SSTL inputs are supported on clock and

DQS pins, while outputs are supported on dedicated

PLL_OUT and DQS

pins. Pseudo-differential HSTL and SSTL I/O standards use two

single-ended outputs with the second output programmed as inverted.

Pseudo-differential HSTL and SSTL inputs treat differential inputs as two

single-ended HSTL and SSTL inputs and only decode one of them. This

I/O support is the same as in Stratix II FPGAs.

The functionality of all DQS circuitry in HardCopy II devices is the same

as in Stratix II FPGAs. Table 2–11 shows the number of DQS/DQ groups

supported in each HardCopy II device density and package.

Table 2–11. DQS and DQ Bus Mode Support (Part 1 of 2)

Device

Package

Number of ×4

Groups

Number of ×8/×9

Groups

Number of

×16/×18 Groups

Number of

×32/×36 Groups

HC210W

484-pin FineLine BGA

(Wire Bond)

HC210

484-pin FineLine BGA

HC220

672-pin FineLine BGA

780-pin FineLine BGA

HC230

1,020-pin FineLine BGA

HC210W Datasheet(PDF) 31 Page - Altera Corporation

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