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HC210W Datasheet(PDF) 74 Page - Altera Corporation

Part # HC210W
Description  HardCopy II Device Family
PDF  228 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

HC210W Datasheet(HTML) 74 Page - Altera Corporation

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Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Differential
SSTL18 class II (5)
8 mA
140
—
—
—
—
140
140
MHz
16 mA
220
—
—
—
—
220
220
MHz
18 mA
220
—
—
—
—
220
220
MHz
20 mA (3)
220
—
—
—
—
220
220
MHz
1.8-V differential
HSTL class I (5)
4 mA
210
—
—
—
—
210
210
MHz
6 mA
210
—
—
—
—
210
210
MHz
8 mA
220
—
—
—
—
220
220
MHz
10 mA
250
—
—
—
—
250
250
MHz
12 mA (3)
270
—
—
—
—
270
270
MHz
1.8-V differential
HSTL class II (5)
16 mA
190
—
—
—
—
190
190
MHz
18 mA
200
—
—
—
—
200
200
MHz
20 mA (3)
210
—
—
—
—
210
210
MHz
1.5-V differential
HSTL class I (5)
4 mA
150
—
—
—
—
150
150
MHz
6 mA
160
—
—
—
—
160
160
MHz
8 mA
170
—
—
—
—
170
170
MHz
10 mA
180
—
—
—
—
180
180
MHz
12 mA (3)
190
—
—
—
—
190
190
MHz
1.5-V differential
HSTL class II (5)
16 mA
170
—
—
—
—
170
170
MHz
18 mA
170
—
—
—
—
170
170
MHz
20 mA (3)
170
—
—
—
—
170
170
MHz
Notes to Table 4–36:
(1)
The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology on
row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from 0 to
5pF.
(2)
CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and excluded from this table.
(3)
This is the default setting in the Quartus II software if supported by the pin location.
(4)
The PCI clamping diode is only supported on the top and bottom I/O pins.
(5)
Like Stratix II devices, differential HSTL and SSTL is supported only on the column
CLK, PLL_OUT and memory
interface
DQS IOE pins. For HC210 and HC220, only the top column clock pins support Differential HSTL and SSTL.
(6)
These numbers are preliminary and pending further silicon characterization.
Table 4–36. HardCopy II Maximum Output Clock Rate for HC210W Devices
Notes (1), (6) (Part 4 of 4)
I/O Standard
Drive
Strength
Memory
Interface
IOEs
High
Speed
IOEs
General Purpose
IOEs
CLK [0,
2, 8,
10] (2)
CLK
[4..7,
12..15]
PLL_OUT
Unit
Bottom
Column
Right
Row



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