HC210W datasheet(9/228 Pages) ALTERA

9 / 228 page

Altera Corporation

2–1

September 2008

Preliminary

2. Description, Architecture,

and Features

Introduction

Altera® HardCopy® II devices feature an architecture that provides

high-density, high-performance, and low-power consumption suitable

for a variety of applications. HardCopy II devices are low-cost structured

ASICs with pin-outs, densities, and architecture that complement

Stratix® II FPGAs. HardCopy II devices make optimal use of die area and

core resources while offering features that are functionally equivalent to

the Stratix II FPGA. The combination of Stratix II FPGAs for in-system

prototype and design verification, HardCopy II devices for high-volume

production, and the Quartus® II design software, provide a complete,

seamless path from prototype to volume production. Table 2–1 provides

an overview of the HardCopy II device features.

Table 2–1. HardCopy II Family Overview (Part 1 of 2)

Feature

HC210W (1)

HC210

HC220

HC230

HC240

ASIC gates (2)

1,000,000

1,900,000

2,900,000

3,600,000

M4K RAM blocks (4k

bits plus parity)

190

408

614

768 (3)

M-RAM blocks (512k

bits plus parity)

Total RAM bits

(including parity bits)

875,520

3,059,712

6,368,256

8,847,360

Enhanced PLLs

Fast PLLs

Package (maximum

user I/O pins) (4), (5)

484-pin

FineLine

BGA (308)

484-pin

FineLine BGA

(334)

672-pin

FineLine BGA

(492)

780-pin

FineLine BGA

(494)

1,020-pin

FineLine BGA

(698)

1,020-pin

FineLine BGA

(742)

1,508-pin

FineLine BGA

(951)

H51016-2.5

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