HC210W datasheet(29/228 Pages) ALTERA

29 / 228 page

Altera Corporation

2–21

September 2008

Preliminary

I/O Structure and Features

provide the same features as the general purpose IOEs except for the PCI

clamping diode. In Stratix II FPGAs, all IOEs support the general purpose

IOE features except the PCI diode, which is only supported on the top

and bottom I/O pins.

The general purpose IOE has many features, including:

■

Dedicated single-ended I/O buffers

■

3.3-V, 64-bit, 66 MHz PCI compliance

■

3.3-V, 64-bit, 133 MHz PCI-X 1.0 compliance

■

JTAG boundary-scan test (BST) support

■

On-chip driver series termination (non-calibrated)

■

Output drive strength control

■

Tri-state buffers

■

Bus-hold circuitry

■

Programmable pull-up resistors

■

Open-drain outputs

■

PCI clamping diode (supported on the bottom I/O pins only)

■

Double data rate (DDR) registers

General purpose IOEs support the following I/O standards:

■

3.3-V LVTTL/LVCMOS

■

2.5-V LVTTL/LVCMOS

■

1.8-V LVTTL/LVCMOS

■

1.5-V LVCMOS

■

3.3-V PCI

■

3.3-V PCI-X mode 1

The general purpose

CLK and PLL_FB input pins and the PLL_OUT

output pins support the following I/O standards:

■

LVDS

■

HyperTransport technology

■

LVPECL (on input clocks and

PLL_OUT only)

The programmable drive strengths available vary depending on the I/O

standard being used and are listed in Table 2–10.

Table 2–10. Programmable Drive Strength Support for General-Purpose

IOEs (Part 1 of 2)

I/O Standard

Programmable Drive Strength Options (mA)

3.3-V LVTTL

4, 8, 12

3.3-V LVCMOS

4, 8

2.5-V LVTTL/LVCMOS

4, 8, 12

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