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HC210W Datasheet(PDF) 83 Page - Altera Corporation |
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HC210W Datasheet(HTML) 83 Page - Altera Corporation |
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83 / 228 page  Altera Corporation 4–41 September 2008 PLL Timing Specifications Table 4–43. HardCopy II Fast PLL Specifications (Part 1 of 2) Name Description Min Typ Max Unit fIN Input clock frequency for HC210, HC220, HC230 and HC240 devices 16 — 717 MHz Input clock frequency for the HC210W device 16 — 320 (1) MHz fINPFD Input frequency to the PFD 16 — 500 MHz fINDUTY Input clock duty cycle 40 — 60 % tINJITTER Input clock jitter tolerance in terms of period jitter. Bandwidth ≤ 2MHz —0.5 — ns (pp) Input clock jitter tolerance in terms of period jitter. Bandwidth > 0.2 MHz —1 — ns (pp) fVCO Upper VCO frequency range for HC210, HC220, HC230 and HC240 devices 300 — 1,040 MHz Upper VCO frequency range for HC210W devices 300 — 840 MHz Lower VCO frequency range for HC210, HC220, HC230 and HC240 devices 150 — 520 MHz Lower VCO frequency range for HC210W device 150 — 420 MHz fOUT PLL output frequency to GCLK or RCLK 4.6875 — 550 MHz PLL output frequency to LVDS or DPA clock for HC210, HC220, HC230 and HC240 devices 150 — 1,040 MHz PLL output frequency to LVDS or DPA clock for HC210W devices 150 — 840 MHz fOUT_IO PLL clock output frequency to regular I/O pin 4.6875 — (1) MHz tCONFIGPLL Time required to reconfigure scan chains for fast PLLs —75/fSCANCLK —ns fCLBW PLL closed loop bandwidth 1.16 5 28 MHz tLOCK Time required for the PLL to lock from the time it is enabled or the end of the device configuration —0.03 1 ms tPLL_PSERR Accuracy of PLL phase shift — — ± 30 ps tARESET Minimum pulse width on areset signal. 10 — — ns |
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