HC210W datasheet(81/228 Pages) ALTERA

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Altera Corporation

4–39

September 2008

PLL Timing Specifications

PLL Timing

Specifications

Tables 4–42 and 4–43 describe the HardCopy II PLL specifications when

operating in both the commercial junction temperature range (0° to 85° C)

and the industrial junction temperature range (–40° to 100° C), except for

the clock switchover feature. Like the Stratix II devices, the clock

switchover feature is only supported from the 0° to 100° C junction

temperature range.

Table 4–42. HardCopy II Enhanced PLL Specifications (Part 1 of 2)

Name

Description

Min

Typ

Max

Unit

fIN

Input clock frequency for HC210,

HC220, HC230 and HC240 devices

—

500

MHz

Input clock frequency for the

HC210W device

—

320 (1)

MHz

fINPFD

Input frequency to the PFD

—

420

MHz

fINDUTY

Input clock duty cycle

—

fEINDUTY

External feedback input clock duty

cycle

—

tINJITTER

Input or external feedback clock

input jitter tolerance in terms of

period jitter. Bandwidth

≤ 0.85 MHz

—0.5

—

(pp)

Input or external feedback clock

input jitter tolerance in terms of

period jitter. Bandwidth > 0.85 MHz

—1

—

(pp)

tOUTJITTER

Dedicated clock output period jitter

for HC210, HC220, HC230 and

HC240 devices

——

250 ps for

≥ 100 MHz

outclk

25 mUI for < 100 MHz

outclk

ps or

mUI

Dedicated clock output period jitter

for HC210W device

——

300 ps for

≥ 100 MHz

outclk

30 mUI for < 100 MHz

outclk

ps or

mUI

tFCOMP

External feedback compensation

time

—

fOUT

Output frequency for internal global

or regional clock

1.5 (2)

—

550

MHz

tOUTDUTY

Duty cycle for external clock output

(when set to 50%).

fSCANCLK

Scanclk frequency

—

100

MHz

tCONFIGEPLL

Time required to reconfigure scan

chains for enhanced PLLs

—

174/fSCANCLK

—ns

fOUT_EXT

PLL external clock output

frequency

1.5 (2)

—

(1)

MHz

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