HC240 datasheet(21/228 Pages) ALTERA

21 / 228 page

Altera Corporation

2–13

September 2008

Preliminary

PLLs and Clock Networks

PLL functionality in HardCopy II devices remains the same as in Stratix II

FPGA PLLs. Therefore, the HardCopy II PLLs support PLL

reconfiguration (the PLL can be dynamically configured in user mode).

HardCopy II enhanced and fast PLLs support a one-to-one mapping from

Stratix II PLL resources. Table 2–7 shows the features of the different

PLLs. For more information on the Stratix II PLL features, refer to the

Stratix II Device Handbook.

Table 2–7. HardCopy II PLL Features

Feature

Enhanced PLL

Fast PLL

Clock multiplication and division

m/(n × post-scale counter) (1)

m/(n × post-scale counter) (2)

Phase shift

Down to 125-ps increments (3)

Clock switchover

vv (4)

PLL reconfiguration

Reconfigurable bandwidth

Spread-spectrum clocking

Programmable duty cycle

Number of clock outputs per PLL (5)

Number of dedicated external clock outputs

per PLL

Three differential or six singled-

ended

(6)

Number of feedback clock inputs per PLL

1 (7)

Notes to Table 2–7:

(1)

For enhanced PLLs, m and n range from 1 to 512 and post-scale counters range from 1 to 512 with 50% duty cycle.

For non-50% duty-cycle clock outputs, post-scale counters range from 1 to 256.

(2)

For fast PLLs, n can range from 1 to 4. The post-scale and m counters range from 1 to 32. For non-50% duty-cycle

clock outputs, post-scale counters range from 1 to 16.

(3)

The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by eight. The

supported phase shift range is from 125 to 250 ps. HardCopy II devices can shift all output frequencies in

increments of at least 45

°. Smaller degree increments are possible depending on the frequency and divide

parameters. For non-50% duty cycle clock outputs post-scale counters range from 1 to 256.

(4)

HardCopy II fast PLLs only support manual clock switchover.

(5)

The clock outputs can be driven to internal clock networks or to a pin.

(6)

The PLL clock outputs of the fast PLLs can drive to any I/O pin to be used as an external clock output. For

high-speed differential I/O pins, the device uses a data channel to generate the transmitter output clock

(

txclkout

(7)

If the design uses external feedback input pins, you will lose one (or two, if fBIN is differential) dedicated external

clock output pin.

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