TMS320 datasheet(62/69 Pages) TI

62 / 69 page

TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77001

Address Stable

Address N + 1

Data In Stable

Data Out Valid

HI-Z

Program

Verify

VIH

VIL

VIH/VOH

VIL/VOL

VPP

VCC

VCC + 1

VCC

VIH

VIL

VIH

VIL

VIH

VIL

A12-A0

Q8-Q1

VPP

VCC

PGM

Figure 11. Fast Programming Timing

program inhibit

Programming may be inhibited by maintaining a high level input on the E pin or PGM pin.

read

The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect

bit) has not been programmed. The read is accomplished by setting E to zero and pulsing G low. The contents

of the EPROM location selected by the value on the address inputs appear on Q8-Q1.

output disable

During the EPROM programming process, the EPROM data outputs may be disabled, if desired, by establishing

the output disable state. This state is selected by setting the G and PGM pins high. While output disable is

selected, Q8-Q1 are placed in the high-impedance state.

ROM protection and verification

This section describes the code protection feature included in the EPROM cell, which protects code against

The paragraphs following the table describe the protect and verify functions.

TMS320 Datasheet(PDF) 62 Page - Texas Instruments

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