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TMS320 Datasheet(PDF) 37 Page - Texas Instruments |
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TMS320 Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 69 page ![]() TMS320C25-50 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 37 MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER MIN TYP MAX UNIT td(C1-S) STRB from CLKOUT (if STRB is present) Q – 5 Q + 3 ns td(C2-S) CLKOUT2 to STRB (if STRB is present) – 2 5 ns tsu(A) Address setup time before STRB low (see Note 5) Q – 11 ns tn(A) Address hold time after STRB high (see Note 5) Q – 4 ns tw(SL) STRB low pulse duration (no wait states, see Note 6) 2Q – 5 2Q + 2 ns tw(SH) STRB high pulse duration (between consecutive cycles, see Note 6) 2Q – 2 2Q + 5† ns tsu(D)W Data write setup time before STRB high (no wait) 2Q – 17 ns th(D)W Data write hold time from STRB high Q – 5 ns ten(D) Data bus starts being driven after STRB low (write) 0 † ns tdis(D) Data bus high-impedance state after STRB high, (write) Q Q + 15† ns td(MSC) MSC valid from CLKOUT1 –1 9 ns † Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C) 5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”. 6. Delay between CLKOUT1, CLKOUT2, and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait states. timing requirements over recommended operating conditions (see Note 3) MIN NOM MAX UNIT ta(A) Read data access time from address time (see Notes 5 and 7) 3Q – 30 ns tsu(D)R Data read setup time before STRB high 19 ns th(D)R Data read hold time from STRB high 0 ns td(SL-R) READY valid after STRB low (no wait states) Q – 21 ns td(C2H-R) READY valid after CLKOUT2 high Q – 21 ns th(SL-R) READY hold time after STRB low (no wait states) Q – 1 ns th(C2H-R) READY valid after CLKOUT2 high Q – 1 ns td(M-R) READY valid after MSC valid 2Q – 24 ns th(M-R) READY hold time after MSC valid 0 ns NOTES: 3. Q = 1/4 tc(C) 5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”. 7. Read data access time is defined as ta(A) = tsu(A) + tw(SL) – tsu(D)R. |
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