TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995

37

POST OFFICE BOX 1443

communication-port byte-cycle timing (write and read) (see Note 14 and Figure 24)

NO

TMS320C44 - 50

TMS320C44 - 60

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

1

tsu(CD-CSL)W

Setup time, CxDx valid before CSTRBx low (write)

2

2

ns

2

td(CRDYL - CSH)W

Delay time, CRDYx low to CSTRBx high (write)

0†

12

0†

12

ns

3

th(CRDYL - CD)W

Hold time, CxDx after CRDYx low (write)

2

2

ns

4

td(CRDYH - CSL)W

Delay time, CRDYx high to CSTRBx low for subsequent bytes

(write)

0†

12

0†

12

ns

5

tc(BYTE)‡

Cycle time, byte transfer

44§

44§

ns

6

td(CSL - CRDYL)R

Delay time, CSTRBx low to CRDYx low (read)

0†

10

0†

10

ns

7

tsu(CSL - CD)R

Setup time, CxDx valid after CSTRBx low (read)

0

0

ns

8

th(CRDYL - CD)R

Hold time, CxDx valid after CRDYx low (read)

2

2

ns

9

td(CSH - CRDYH)R

Delay time, CSTRBx high to CRDYx high (read)

0†

10

0†

10

ns

† This value is specified by design but not tested.

‡ tc(BYTE) max = summed maximum values of td(CRDY-CSH), td(CSL-CRDYL)R, td(CSH-CRDYH)R, and td(CRDYH-CSL)W. This assumes

two ’C4xs are connected.

§ This value is characterized but not tested.

NOTE 14: Communication port timing does not include line length delay.

CREQx

CACKx

CSTRBx

CxDx

CRDYx

(a) WRITE TIMING

(b) READ TIMING

Valid

Data

1

4

7

6

8

2

3

5

9

5

= When signal is an input (clear = when signal is an output).

Figure 24. Communication-Port Byte-Cycle Timing (Write and Read)