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TMS320C44 Datasheet(PDF) 32 Page - Texas Instruments

Part # TMS320C44
Description  DIGITAL SIGNAL PROCESSOR
PDF  42 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320C44 Datasheet(HTML) 32 Page - Texas Instruments

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TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
timing of IIOFx changing from input to output mode (see Figure 19)
NO
TMS320C44- 50
TMS320C44- 60
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
1
td(H1L - IFIO)
Delay time, H1 low to IIOFx switching from input to output
14
14
ns
Execution of
Load of IIF
Register
1
H3
H1
TYPEx
(IIF Register)
IIOFx
Figure 19. Change of IIOFx From Input to Output Mode
RESET timing (see Figure 20)
NO
TMS320C44- 50
TMS320C44- 60
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
1
tsu(RESET-C1L)
Setup time for RESET before CLKIN low
11
tc(CI)
11
tc(CI)
ns
2.1
td(CIH - H1H)
Delay time, CLKIN high to H1 high
2
10
2
10
ns
2.2
td(CIH - H1L)
Delay time, CLKIN high to H1 low
2
10
2
10
ns
3
tsu(RESETH - H1L)
Setup time for RESET high before H1 low and after ten H1
clock cycles
13
13
ns
4.1
td(CIH - H3L)
Delay time, CLKIN high to H3 low
2
10
2
10
ns
4.2
td(CIH - H3H)
Delay time, CLKIN high to H3 high
2
10
2
10
ns
5
td(H1H - DZ)
Delay time, H1 high to (L)Dx in the high-impedance state
13†
13†
ns
6
td(H3H - AZ)
Delay time, H3 high to (L)Ax in the high-impedance state
9†
9†
ns
7
td(H3H - CONTROLH)
Delay time, H3 high to control signals high [low for (L)PAGE]
9†
9†
ns
8
td(H1H - IACKH)
Delay time, H1 high to IACK high
9†
9†
ns
9
td(RESETL - ASYNCH)
Delay time, RESET low to asynchronous reset signals in the
high-impedance state
21†
21†
ns
10
td(RESETH - COMMH)
Delay time, RESET high to asynchronous reset signals high
15†
15†
ns
11
td(H1H-CDIRL)
Delay time,
9
9
ns
12
td(H1H-CDIRH)
Delay time,
9
9
ns
† This value is characterized but not tested.



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