TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995

35

POST OFFICE BOX 1443

timing for IACK (see Note 12 and Figure 22)

NO

TMS320C44 - 50

TMS320C44 - 60

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

1

td(H1L - IACKL)

Delay time, H1 low to IACK low

9

7

ns

2

td(H1L - IACKH)

Delay time, H1 low to IACK high during first cycle of IACK instruction

data read

9

7

ns

NOTE 12: The IACK output is active for the entire duration of the bus cycle and is, therefore, extended if the bus cycle utilizes wait states.

H3

H1

IACK

Address

Data

12

Fetch IACK

Instruction

IACK Data

Read

Decode IACK

Instruction

Execute IACK

Instruction

Figure 22. IACK Timing