TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995

38

POST OFFICE BOX 1443

NO.

MIN

MAX

UNIT

1‡

td(CAL - CS)T

Delay time, CACKx low to CSTRBx change from input to a high-level output

0.5P+ 6

1.5P + 22

ns

2‡

td(CAL - CRQH)T

Delay time, CACKx low to start of CREQx going high for token-request

acknowledge

P+5

2P + 22

ns

3

td(CRQH - CRQ)T

Delay time, start of CREQx going high to CREQx change from output to an input

0.5P – 5

0.5P + 13

ns

4

td(CRQH - CA)T

Delay time, start of CREQx going high to CACKx change from an input- to an

output-level high

0.5P – 5

0.5P + 13

ns

4.1

td(CRQH - CD)T

Delay time, start of CREQx going high to CxDx change from input-driven to

output-driven

0.5P – 5

0.5P + 13

ns

4.2

td(CRQH - CRDY)T

Delay time, start of CREQx going high to CRDYx change from an output to an

input

0.5P – 5

0.5P + 13

ns

5

td(CRQH - CSL)T

Delay time, start of CREQx going high to CSTRBx low for start of word-transfer

out

1.5P – 8

1.5P + 9

ns

6

td(CRDYL - CSL)T

Delay time, CRDYx low at end of word-input to CSTRBx low for word-output

3.5P + 12

5.5P + 48

ns

7

td(CRQH - CDIRL)

Delay time, CREQx high to CDIRx low, change from input to output

0.5P – 5

0.5P + 13

ns

† These values are characterized but not tested.

‡ These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal

pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the

maximum delay occurs when the input condition occurs just after H1 falling.

CREQx

CACKx

CSTRBx

CxDx

CRDYx

= When signal is an input (clear = when signal is an output).

6

3

4

1

4.1

4.2

Valid Data Out

2

5

CDIRx

7

NOTE A: Before the token exchange, CREQx and CRDYx are output signals asserted by the ’320C44 receiving data. CACKx, CSTRBx, and

CxD7 – CxD0 are input signals asserted by the device sending data to the ’C44; these are asynchronous with respect to the H1 clock

of the receiving ’320C44. After token exchange, CACKx, CSTRBx, and CxD7 – CxD0 become output signals, and CREQx and CRDYx

become inputs.